High-speed serial implementations are frequently utilized for computer internal data communications. Examples include, but are not limited to, PCI Express, Serial Attached SCSI, and Serial ATA. Such serial implementations generally utilize packet-based interfaces. Within the integrated circuits that implement such interfaces, serial bit streams are converted into parallel packet-based data streams (e.g. data bus) in order to reduce internal clock rates to manageable frequencies. As the speeds of such serial interfaces increase, widths of the packet-based data streams may be increased accordingly to keep clock speeds reasonable. In such implementations, it is common for an interface to allow a packet to start with any byte alignment on the data bus. It is also common that packet transmissions are not synchronized with the internal clock, i.e., a packet-based transmission may start and end at any time relative to the internal clock.